Title :
A new integrated test structure for on-chip post-irradiation annealing in MOS devices
Author :
Chabrerie, C. ; Autran, J.L. ; Lament, O.F. ; Boudenot, J.C.
Author_Institution :
Thomson-CSF, Colombes, France
fDate :
6/1/1998 12:00:00 AM
Abstract :
We have developed a prototype test structure (named THERMOS) demonstrating the feasibility and the interest of the on-chip heating in a Silicon-On-Insulator technology. This circuit has been specially designed for the study of post-irradiation effects in a radiation-hardened CMOS technology. Preliminary results are presented here for the on-chip annealing of irradiated n-channel transistors
Keywords :
MOSFET; annealing; radiation hardening (electronics); semiconductor device testing; silicon-on-insulator; CMOS SOI technology; MOS device; THERMOS; integrated test structure; n-channel transistor; on-chip post-irradiation annealing; radiation hardening; Annealing; Circuit testing; Fabrication; Heating; MOS devices; MOSFETs; Packaging; Resistors; Silicon; Temperature;
Journal_Title :
Nuclear Science, IEEE Transactions on
