DocumentCode
1394839
Title
A new integrated test structure for on-chip post-irradiation annealing in MOS devices
Author
Chabrerie, C. ; Autran, J.L. ; Lament, O.F. ; Boudenot, J.C.
Author_Institution
Thomson-CSF, Colombes, France
Volume
45
Issue
3
fYear
1998
fDate
6/1/1998 12:00:00 AM
Firstpage
1438
Lastpage
1443
Abstract
We have developed a prototype test structure (named THERMOS) demonstrating the feasibility and the interest of the on-chip heating in a Silicon-On-Insulator technology. This circuit has been specially designed for the study of post-irradiation effects in a radiation-hardened CMOS technology. Preliminary results are presented here for the on-chip annealing of irradiated n-channel transistors
Keywords
MOSFET; annealing; radiation hardening (electronics); semiconductor device testing; silicon-on-insulator; CMOS SOI technology; MOS device; THERMOS; integrated test structure; n-channel transistor; on-chip post-irradiation annealing; radiation hardening; Annealing; Circuit testing; Fabrication; Heating; MOS devices; MOSFETs; Packaging; Resistors; Silicon; Temperature;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/23.685220
Filename
685220
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