• DocumentCode
    1394899
  • Title

    Tunable SEU-Tolerant Latch

  • Author

    She, Xiaoxuan ; Li, N. ; Farwell, W. Darresware

  • Author_Institution
    State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
  • Volume
    57
  • Issue
    6
  • fYear
    2010
  • Firstpage
    3787
  • Lastpage
    3794
  • Abstract
    This paper presents a single event upset (SEU) hardened latch that can mitigate SEU pulses having a width less than T, where T is the longest anticipated duration of SEUs. The propose latch includes a controllable inertial delay inverter. In order to mitigate SEUs with pulse widths less than T, a global controller uses delay locked loops to control the rise and fall times of the controllable inertial delay inverter in each latch to be equal to T. This allows T to be adjustable for different applications and environmental conditions. This technique introduces little area penalty and does not adversely affect propagation delay.
  • Keywords
    flip-flops; logic gates; nuclear electronics; radiation hardening (electronics); SEU hardened latch; SEU pulses mitigation; area penalty; controllable inertial delay inverter; delay locked loops; global controller; propagation delay; pulse widths; single event upset; tunable SEU-tolerant latch; Latches; Radiation effects; Single event upset; Hardened by design; latch; radiation effects; single event upset (SEU);
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2010.2087358
  • Filename
    5658075