High voltage silicon power device structure with substrate bias

A new high voltage silicon LDMOS structure with substrate bias is reported (SB S-LDMOS). The vertical conduction path is blocked by the double p^-/n⁺ layer substrate when positive substrate bias is applied to the SB S-LDMOS. The bulk electric field in the drift region redistributes by substrate bias and the vertical voltage sustained by the depletion region under drain decreases significantly, which is especially important for a thin drift region power device. Numerical results indicate that the breakdown voltage of the proposed device is increased by 94% compared to conventional LDMOS, while maintaining low on-resistance.