• DocumentCode
    1395025
  • Title

    A low-complexity power-sum circuit for GF(2m) and its applications

  • Author

    Guo, Jyh-Huei ; Wang, Chin-Liang

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • Volume
    47
  • Issue
    10
  • fYear
    2000
  • fDate
    10/1/2000 12:00:00 AM
  • Firstpage
    1091
  • Lastpage
    1097
  • Abstract
    This brief presents a new hardware-efficient bit-parallel circuit for computing C+AB2 in finite fields GF(2m) over the canonical basis. It consists of two parts: a normal poser-sum part and modular-reduction part, where each part is realized in a binary XOR tree structure. The proposed power-sum circuit works for the general-form generating polynomial and requires 3 m2-2 m AND gates and 3 m2-4 m+2 XOR gates to reach low time complexity of O(log2 m). As compared to the conventional cellular-array structures for C+AB2 in GF(2m), the proposed one involves less hardware complexity and achieves a significant reduction in time complexity. The hardware requirement can further be reduced when a special-form generating polynomial is adopted. The corresponding reduced structures based on three special-form generating polynomials, including the trinomial xm+x+1, the all-one polynomial, and the equally spaced polynomial, are given to demonstrate this property. A versatile structure, which can be programmed to compute inverses/divisions and exponentiations in GF(2m), is also constructed based on the proposed power-sum circuit
  • Keywords
    computational complexity; digital arithmetic; parallel architectures; polynomials; GF(2m) and its applications; all-one polynomial; binary XOR tree structure; canonical basis; equally spaced polynomial; exponentiations; finite fields; general-form generating polynomial; hardware complexity; hardware-efficient bit-parallel circuit; low-complexity power-sum circuit; modular-reduction part; normal poser-sum part; power-sum circuit; special-form generating polynomial; special-form generating polynomials; time complexity; Circuits; Clocks; Computer architecture; Concurrent computing; Delay; Error correction codes; Galois fields; Hardware; Polynomials; Tree data structures;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7130
  • Type

    jour

  • DOI
    10.1109/82.877151
  • Filename
    877151