Module implementation selection and its application to transistor placement

In this paper, we present an algorithm for selecting implementations for rectangular modules given a placement of the modules in multiple rows. A module is a rectangle with pins located on the top and the bottom edges. An implementation of a module is specified by its dimension and a placement of the pins along the top and bottom edges of the module. Our algorithm accepts as input a placement of the modules and a set of possible implementations of each module, and selects an implementation for each module to minimize the total height of the layout. The time complexity of our algorithm is O(NrK^r+K²P), where K is the maximum number of implementations for each module, r is the number of rows, N is the total number of modules, and P is the number of pins in the channel. Our algorithm can be applied to the CMOS transistor placement, and has been implemented in the custom cell synthesis system of MCC. We have tested the algorithm on cells selected from the MCNC benchmarks and industry. Reductions of up to 19% in layout area were obtained