• DocumentCode
    1395042
  • Title

    Planar topological routing

  • Author

    Lim, Andrew ; Thanvantri, Venkat ; Sahni, Sartaj

  • Author_Institution
    Inf. Technol. Inst., Nat. Comput. Board, Singapore
  • Volume
    16
  • Issue
    6
  • fYear
    1997
  • fDate
    6/1/1997 12:00:00 AM
  • Firstpage
    651
  • Lastpage
    656
  • Abstract
    We develop a simple linear time algorithm to determine if a collection of two-pin nets can be routed, topologically, in a plane (i.e., single layer). Experiments indicate that this algorithm is faster than the linear time algorithm of Marek-Sadowska and Tarng. Topological routability testing of a collection of multipin nets is shown to be equivalent to planarity testing, and a simple linear time algorithm is developed for the case when the collection of modules remains connected following the deletion of all nets with more than two pins
  • Keywords
    algorithm theory; circuit layout CAD; integrated circuit layout; network routing; network topology; linear time algorithm; multipin nets; planar topological routing; planarity testing; topological routability testing; two-pin nets; Information technology; Integrated circuit interconnections; Pins; Rivers; Routing; Shape; Switches; Testing; Two dimensional displays; Wire;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.640623
  • Filename
    640623