Design of the lower error fixed-width multiplier and its application

This brief develops a general methodology for designing a lower-error two´s-complement fixed-width multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index, we derive better error-compensation bias to reduce the truncation error and then construct a lower error fixed-width multiplier, which is area efficient for VLSI implementation. Finally, we successfully apply the proposed fixed-width multiplier to realizing a digital FIR filter, which has shown that the performance is better than that using other fixed-width multipliers