• DocumentCode
    1395226
  • Title

    Silicon-on-Nothing (SON)-an innovative process for advanced CMOS

  • Author

    Jurczak, Malgorzata ; Skotnicki, Thomas ; Paoli, M. ; Tormen, B. ; Martins, J. ; Regolini, Jorge Luis ; Dutartre, Didier ; Ribot, Pascal ; Lenoble, D. ; Pantel, Roland ; Monfray, Stephanie

  • Author_Institution
    France Telecom, CNET Grenoble, Meylan, France
  • Volume
    47
  • Issue
    11
  • fYear
    2000
  • fDate
    11/1/2000 12:00:00 AM
  • Firstpage
    2179
  • Lastpage
    2187
  • Abstract
    A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guaranteed by epitaxial process. The SON process´ allows the buried dielectric (which may be an oxide but also an-air gap) to be fabricated locally in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device, thus enabling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies the ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON enable ables excellent Ion/Ioff trade-off, suppressed self-heating, low S/D series resistance, close to ideal subthreshold slope, and high immunity to SCE and DIBL down to ultimate device dimensions of 30 to 50 nm
  • Keywords
    CMOS integrated circuits; buried layers; dielectric thin films; integrated circuit technology; semiconductor epitaxial layers; silicon; CMOS device architecture; DIBL immunity; SCE immunity; SON process; Si; epitaxial process; extremely thin buried Si layers; extremely thin buried dielectrics; highly doped drain junctions; highly doped extensions; low S/D series resistance; self-heating suppression; shallow extensions; silicon on nothing process; subthreshold slope; system-on-chip integration; CMOS process; Costs; Dielectric devices; Dielectric films; Dielectric thin films; MOSFET circuits; Microelectronics; Semiconductor films; Silicon; Telecommunications;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.877181
  • Filename
    877181