IIR digital filter design using minimum adder multiplier blocks

Author

Dempster, A.G. ; Macleod, M.D.

Author_Institution

Sch. of Electron. & Manuf. Syst., Westminster Univ., London, UK

Volume

Issue

fYear

1998

fDate

6/1/1998 12:00:00 AM

Firstpage

761

Lastpage

763

Abstract

Traditional methods for the design of fixed-point IIR filters suggest the use of wave filters to reduce complexity. The application of multiplier blocks, which exploit redundancy across the coefficients, changes the relationships between structures such that the cascade structure is most efficient. The use of variable wordlength methods results in further complexity reduction

Keywords

IIR filters; digital arithmetic; digital filters; filtering theory; limit cycles; multiplying circuits; redundancy; wave digital filters; IIR digital filter design; cascade structure; complexity reduction; fixed-point IIR filters; minimum adder multiplier blocks; redundancy; variable wordlength methods; Added delay; Adders; Application specific integrated circuits; Costs; Design methodology; Digital filters; IIR filters; Integrated circuit measurements; Limit-cycles; Performance evaluation;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.686699

Filename

686699

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1395826