Title :
IIR digital filter design using minimum adder multiplier blocks
Author :
Dempster, A.G. ; Macleod, M.D.
Author_Institution :
Sch. of Electron. & Manuf. Syst., Westminster Univ., London, UK
fDate :
6/1/1998 12:00:00 AM
Abstract :
Traditional methods for the design of fixed-point IIR filters suggest the use of wave filters to reduce complexity. The application of multiplier blocks, which exploit redundancy across the coefficients, changes the relationships between structures such that the cascade structure is most efficient. The use of variable wordlength methods results in further complexity reduction
Keywords :
IIR filters; digital arithmetic; digital filters; filtering theory; limit cycles; multiplying circuits; redundancy; wave digital filters; IIR digital filter design; cascade structure; complexity reduction; fixed-point IIR filters; minimum adder multiplier blocks; redundancy; variable wordlength methods; Added delay; Adders; Application specific integrated circuits; Costs; Design methodology; Digital filters; IIR filters; Integrated circuit measurements; Limit-cycles; Performance evaluation;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
