A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS

Author

Pei-Yao Chang ; Tay-Jyi Lin ; Jinn-Shyan Wang ; Yen-Hsiang Yu

Author_Institution

Dept. of Electr. Eng. & SoC/AIM-HI Centers, Nat. Chung Cheng Univ. (CCU), Chiayi, Taiwan

Volume

59

Issue

12

fYear

2012

Firstpage

908

Lastpage

912

Abstract

This brief presents a 4R/2W register file design for two-issue microprocessors with ultra-wide dynamic voltage scaling. A full-N separated read port has been proposed to save ~ 19% area and to improve 4.5 ~ 10.4 % performance of state-of-the-art 1P3N designs for subthreshold operations. In addition, a reconfigurable write scheme has been proposed to utilize the unused write port in the energy-efficient mode with single-issue execution for ~ 18% write noise margin improvement. A test chip has been designed and fabricated using the TSMC 65-nm GP process, of which a minimum operating voltage of 148 mV has been measured.

Keywords

CMOS digital integrated circuits; microprocessor chips; reconfigurable architectures; shift registers; 4R-2W register file design; CMOS technology; UDVS microprocessors; reconfigurable write scheme; separated read port; size 65 nm; subthreshold operations; test chip; ultrawide dynamic voltage scaling; voltage 148 mV; write noise margin improvement; write port; CMOS integrated circuits; Layout; Low voltage; Microprocessors; Semiconductor device measurement; Threshold voltage; Voltage control; Register file design; subthreshold design; ultra-wide dynamic voltage scaling (UDVS);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2012.2231031

Filename

6407962