DocumentCode :
1396946
Title :
A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator
Author :
Kuo-Hsing Cheng ; Jen-Chieh Liu ; Hong-Yi Huang
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Taoyuan, Taiwan
Volume :
59
Issue :
12
fYear :
2012
Firstpage :
888
Lastpage :
892
Abstract :
This paper proposes an ultra-low-voltage all-digital phase-locked loop (ADPLL) with a digital supply regulator (DSR). The DSR maintains an RMS jitter for a 280-MHz output signal of less than 0.55% when a 100-kHz to 100-MHz supply noise is produced on a digitally controlled oscillator (DCO). The DCO uses the two-step timing resolution of a digitally controlled varactor to achieve the high timing resolution. The proposed digital loop filter can reduce the area cost and critical path using the double-edge trigger technique. For a low supply voltage, the DCO and the time-to-digital converter use bulk-controlled techniques to increase the highest operating frequency and timing resolution, respectively. When the ADPLL output is 800 MHz at 0.6 V, the power consumption and core area are 656 μW and 0.02 mm2, respectively, in a 90-nm CMOS process.
Keywords :
CMOS integrated circuits; convertors; digital phase locked loops; filtering theory; jitter; low-power electronics; mean square error methods; oscillators; power consumption; power supply circuits; varactors; ADPLL; CMOS process; DCO; DSR; RMS jitter; bulk-controlled techniques; core area; critical path; digital loop filter; digital supply regulator; digitally controlled oscillator; digitally controlled varactor; double-edge trigger technique; frequency 100 kHz to 100 MHz; frequency 280 MHz; frequency 800 MHz; high timing resolution; low supply voltage; operating frequency; output signal; power 656 muW; power consumption; size 90 nm; supply noise; time-to-digital converter; two-step timing resolution; ultra-low-voltage all-digital phase-locked loop; voltage 0.6 V; Jitter; Low voltage; Noise measurement; Phase locked loops; Power demand; Regulators; Timing; Varactors; All-digital PLL (ADPLL); digital controlled varactor (DCV); digital loop filter (DLF); digital supply regulator (DSR);
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2012.2231021
Filename :
6407963
Link To Document :
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