DocumentCode :
1397224
Title :
Algorithm-based low-power and high-performance multimedia signal processing
Author :
Liu, K. J Ray ; Wu, An-Yeu ; Raghupathy, Arun ; Chen, Jie
Author_Institution :
Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
Volume :
86
Issue :
6
fYear :
1998
fDate :
6/1/1998 12:00:00 AM
Firstpage :
1155
Lastpage :
1202
Abstract :
Low power and high performance are the two most important criteria for many signal-processing system designs, particularly in real-time multimedia applications. There have been many approaches to achieve these two design goals at many different implementation levels ranging from very-large-scale-integration fabrication technology to system design. We review the works that have been done at various levels and focus on the algorithm-based approaches for low-power and high-performance design of signal processing systems. We present the concept of multirate computing that originates from filterbank design, then show how to employ it along with the other algorithmic methods to develop low-power and high-performance signal processing systems. The proposed multirate design methodology is systematic and applicable to many problems. We demonstrate that multirate computing is a powerful tool at the algorithmic level that enables designers to achieve either significant power reduction or high throughput depending on their choice. Design examples on basic multimedia processing blocks such as filtering, source coding, and channel coding are given. A digital signal-processing engine that is an adaptive reconfigurable architecture is also derived from the common features of our approach. Such an architecture forms a new generation of high-performance embedded signal processor based on the adaptive computing model. The goal of this paper is to demonstrate the flexibility and effectiveness of algorithm-based approaches and to show that the multirate approach is an effective and systematic design methodology to achieve low-power and high throughput signal processing at the algorithmic and architectural level
Keywords :
VLSI; adaptive filters; adaptive signal processing; channel coding; digital filters; digital signal processing chips; filtering theory; multimedia communication; source coding; VLSI fabrication; adaptive computing model; adaptive reconfigurable architecture; algorithm-based approaches; algorithmic methods; channel coding; digital signal-processing engine; embedded signal processor; filterbank design; filtering; high performance system; high throughput; low power system; multimedia processing blocks; multimedia signal processing; multirate computing; power reduction; real-time multimedia applications; signal processing systems; source coding; system design; Algorithm design and analysis; Design methodology; Fabrication; Multimedia systems; Process design; Real time systems; Signal design; Signal processing algorithms; Throughput; Very large scale integration;
fLanguage :
English
Journal_Title :
Proceedings of the IEEE
Publisher :
ieee
ISSN :
0018-9219
Type :
jour
DOI :
10.1109/5.687834
Filename :
687834
Link To Document :
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