A Frequency Model of a Continuously Driven Clocked CMOS Comparator

Author

Okura, Shunsuke ; Shibata, Hajime ; Okura, Tetsuro ; Ido, Toru ; Taniguchi, Kenji

Author_Institution

Grad. Sch. of Eng., Osaka Univ., Suita, Japan

Volume

57

Issue

12

fYear

2010

Firstpage

956

Lastpage

960

Abstract

A frequency model of a continuously driven clocked CMOS comparator with the effect of the input signal during regeneration is presented. The model utilizes a small-signal linear model derived from the theoretical analysis of the comparison error caused by the transition from the tracking mode to the regeneration mode. The comparison error voltage is a function of input signal frequency and is represented with the transfer function. The correctness of the model is assured by several transistor-level simulation results. The model provides a valuable insight for the design of high-speed comparators.

Keywords

CMOS integrated circuits; clocks; comparators (circuits); integrated circuit modelling; transfer functions; comparison error voltage; continuously driven clocked CMOS comparator; frequency model; high-speed comparators; input signal frequency; regeneration mode; small-signal linear model; tracking mode; transfer function; transistor-level simulation results; CMOS integrated circuits; Clocks; Frequency response; Semiconductor device modeling; Simulation; Transfer functions; CMOS; Clocked comparator; frequency response; metastability; regeneration;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2010.2087972

Filename

5659896