Low-power high-efficiency architecture for low-complexity chase soft-decision Reed-Solomon decoding

Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can obtain significant coding gain over the hard-decision decoding with polynomial complexity. Compared with other ASD algorithms, the low-complexity chase (LCC) decoding testing 2^η test vectors has less computation complexity with similar or better coding gain. To reduce the latency of the interpolation, one major step of the LCC decoding, multiple interpolators can be applied and the pipelined architecture is usually adopted to make the throughput of the decoder higher. However, for application specific integrated circuit (ASIC) implementation and practical applications, the area and power consumption of the pipelined decoder are not preferable. This study proposes a modified serial LCC decoder architecture which reduces the power consumption and hardware requirement while keeping the shortest critical path as one adder, one multiplexer and one multiplier. As major contributions of this study, a novel re-encoder and erasure decoder block and an improved way to compute syndromes are proposed to reduce the whole latency of the decoder. For a (458, 410) RS code over Galois Field (GF)(2¹⁰) with η=8, the hardware requirement and power consumption of the proposed LCC decoder are reduced by 23 and 25% than those of the common pipelined counterparts, respectively.