Title :
Neural network architectures for content-addressable memory
Author :
Tarassenko, L. ; Tombs, J.N. ; Reynolds, J.H.
Author_Institution :
Dept. of Eng. Sci., Oxford Univ., UK
fDate :
2/1/1991 12:00:00 AM
Abstract :
Investigates whether neural network content-addressable memories (CAMs) can compete with the non-neural alternatives which are currently available. The storage and retrieval of 64-bit patterns is used as a test problem which reflects the requirements of today´s computer technology. The two main strategies available for implementing a CAM with a neural network architecture, feedback networks and two-stage CAMs, and in particular their ability to retrieve patterns from corrupted input data, are investigated in detail. The storage capacity of the Hopfield network is very poor although it can be improved with the use of an iterative algorithm, such as the threshold algorithm which is described. However, the possibility of generating spurious patterns always remains with feedback networks. Two-stage CAMs are much more efficient, provided that an appropriate algorithm is used for the input classification stage. Perceptron and least-mean squares algorithms need to be modified if they are to cope with corrupted input patterns, but the optimal classifier for the type of problem under consideration is the minimum-distance classifier (or Hamming network for binary patterns). The implementation of the latter in analogue VLSI is discussed
Keywords :
VLSI; content-addressable storage; neural nets; parallel architectures; 64 bit; Hopfield network; analogue VLSI; content-addressable memory; feedback networks; iterative algorithm; least-mean squares; neural network; parallel architectures; pattern classifier; perceptron; storage capacity; threshold algorithm;
Journal_Title :
Radar and Signal Processing, IEE Proceedings F