• DocumentCode
    1397625
  • Title

    A parallel arithmetic unit using a saturated-transistor fast-carry circuit

  • Author

    Kilburn, T. ; Edwards, D.B.G. ; Aspinall, D.

  • Volume
    107
  • Issue
    36
  • fYear
    1960
  • fDate
    11/1/1960 12:00:00 AM
  • Firstpage
    573
  • Lastpage
    584
  • Abstract
    The paper describes a transistor switch technique which is of particular importance in applications where a large number of switches have to be connected in series and where the propagation time of information through these switches has to be a minimum. It is thus of importance in parallel addition, and its use in this connection has been successfully demonstrated, yielding an addition time over 24 digits of 200 millimicrosec. The technique is reasonably economical, and the paper also shows how it can be used in conjunction with more conventional logical circuits to provide a simple arithmetic unit.
  • Keywords
    circuits and sub-assemblies;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEE - Part B: Electronic and Communication Engineering
  • Publisher
    iet
  • ISSN
    0369-8890
  • Type

    jour

  • DOI
    10.1049/pi-b-2.1960.0171
  • Filename
    5244069