A 10 Gb/s ATM data synchronizer

Author

Wong, Thomas Y K ; Sitch, John E.

Author_Institution

Adv. Technol. Lab., Nortel Technol., Ottawa, Ont., Canada

Volume

31

Issue

10

fYear

1996

fDate

10/1/1996 12:00:00 AM

Firstpage

1394

Lastpage

1399

Abstract

Asynchronous transfer mode (ATM) data comes from different sources, and it is by nature bursty, hence causing the incoming phase and exact bit rate to vary from burst to burst. In order to retime the bursty data, a conventional yet low-Q clock recovery scheme could be used, but the downstream system components would have to cope with the consequent clock interruptions and variations in phase and frequency. This work presents a phase agile data synchronizer integrated circuit that retimes bursty ATM cells at 10 Gb/s to an external 10 GHz clock. The integrated circuit comprises an analog variable data delay, a phase detector, an edge detector, a loop filter, and a data retime. It has a total delay range of 200 pS. The integrated circuit has been fabricated in both AlGaAs/GaAs and InGaP/GaAs HBT technology

Keywords

III-V semiconductors; SONET; aluminium compounds; asynchronous transfer mode; bipolar integrated circuits; delays; digital communication; gallium arsenide; gallium compounds; indium compounds; synchronisation; 10 GHz; 10 Gbit/s; 200 ps; ATM data synchronizer; AlGaAs-GaAs; HBT technology; InGaP-GaAs; analog variable data delay; bursty data; edge detector; exact bit rate; incoming phase; phase agility; phase detector; total delay range; Analog integrated circuits; Asynchronous transfer mode; Bit rate; Clocks; Delay; Detectors; Filters; Frequency synchronization; Gallium arsenide; Phase detection;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.540046

Filename

540046