Title :
A high performance 0.35-μm 3.3-V BiCMOS technology optimized for product porting from a 0.6-μm 3.3-V BiCMOS technology
Author :
Banik, Jashojiban ; Wong, Keng L. ; Geannopoulos, George L. ; Yip, Chung Y Joseph
Author_Institution :
Intel Corp., Hillsboro, OR, USA
fDate :
10/1/1996 12:00:00 AM
Abstract :
A 0.35-μm logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5-V version offers lower power and higher performance. A 3.3-V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6-μm 3.3-V BiCMOS process. A two-step design process for converting an existing production worthy 0.6-μm 3.3-V BiCMOS design to a 0.35-μm design is described. The silicon results are described
Keywords :
BiCMOS digital integrated circuits; integrated circuit design; integrated circuit reliability; integrated circuit technology; 0.35 micron; 3.3 V; BiCMOS technology; Si; compatibility; logic technology; planarized metal interconnect; product porting; two-step design process; BiCMOS integrated circuits; Clocks; Current density; Design optimization; Driver circuits; Integrated circuit interconnections; Logic; Optimized production technology; Process design; Silicon;
Journal_Title :
Solid-State Circuits, IEEE Journal of
