Title :
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry
Author :
Higeta, Keiichi ; Usami, Masami ; Ohayashi, Masayuki ; Fujimura, Yasuhiro ; Nishiyama, Masahiko ; Isomura, Satoru ; Yamaguchi, Kunihiko ; Idei, Youji ; Nambu, Hiroaki ; Ohhata, Kenichi ; Hanta, Nadateru
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
fDate :
10/1/1996 12:00:00 AM
Abstract :
A soft-error-immune, 0.9-ns address access time, 2.0-ns read/write cycle time, 1.15-Mb emitter coupled logic (ECL)-CMOS SRAM with 30-ps 120 k ECL and CMOS logic gates has been developed using 0.3-μm BiCMOS technology. Four key developments ensuring good testability, reliability, and stability are on-chip test circuitry for precise measurement of access time and for multibit parallel testing, a memory-cell test technique for an ECL-CMOS SRAM, a highly stable current source with a simple design using a current mirror, and a soft-error-immune memory cell using a silicon-on-insulator (SOI) wafer. These techniques will be especially useful for making the ultrahigh-speed, high-density SRAM´s used as cache and control storages in mainframe computers
Keywords :
BiCMOS memory circuits; SRAM chips; built-in self test; cache storage; circuit stability; emitter-coupled logic; integrated circuit reliability; integrated circuit testing; 0.3 micron; 0.9 ns; 1.15 Mbit; 2.0 ns; 30 ps; ECL-CMOS SRAM; SOI wafer; address access time; cache storage; control storage; current mirror; current source; memory-cell test technique; multibit parallel testing; on-chip test circuitry; read/write cycle time; reliability; soft-error-immune circuits; stability; testability; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit stability; Circuit testing; Coupling circuits; Current measurement; Logic gates; Random access memory; Time measurement;
Journal_Title :
Solid-State Circuits, IEEE Journal of
