Abstract :
Neural networks and related techniques are powerful tools that prove their efficiency in real-world applications, where problems are badly defined or difficult to formalize. Some applications, especially those involving images, require a huge number of operations and an enormous reduction of the dataflow from input to output data. For sorting objects by vision or image analysis, for example, inputs are images at video rate; outputs are correcting values, names of objects, or locations of specific objects in a picture. For several years, our group has been involved in image-processing applications, mainly with connectionist algorithms such as neural networks, that enable efficient use of parallel hardware. We designed and tested our first-generation processor, L-Neuro 1.0, on shape recognition with neural networks and image compression applications. However, unlike L-Neuro 1.0 and chips such as Intel´s NI 1000 and IBMs ZISC, our newest processor, L-Neuro 2.3, is a multiDSP. It exhibits full general-purpose vector processing capabilities, like Siemens´ MA16, Adaptive Solutions´ CNAPS, Mitsubishi´s Neuro 4, and AT&T´s HIP. This fully programmable vector processor uses an array of 12 digital signal processors to perform up to 2 billion arithmetic operations per second and achieve a peak transfer throughout of 2 Gbytes/s for image-processing applications
Keywords :
digital signal processing chips; image processing; neural net architecture; neural nets; reduced instruction set computing; L-Neuro 1.0; L-Neuro 2.3; connectionist algorithms; image compression; image processing; multiDSP; neural networks; shape recognition; vector processing; Image analysis; Image coding; Image processing; Image recognition; Neural network hardware; Neural networks; Shape; Signal processing algorithms; Sorting; Testing;