Abstract :
Diffusion techniques are employed in transistor technology for cases where, for instance, a graded impurity profile improves the frequency response of alloyed structures, or for accurate control in the manufacture of very narrow base regions. This practice leads generally to a very low emitter-base breakdown voltage due to the high impurity density facing the emitter. This limitation can be overcome by insertion of a layer of high resistivity between the emitter and the graded base. The current flow equations of such a structure are derived for the case when charge neutrality prevails over a considerable part of the interposed layer, and the somewhat lowered frequency response is calculated. The signal delay time due to this neutral layer is shown to be proportional to (current density)¿¿, so that the emitter has to be adequately forward-biased. Several devices with varying design aims are evaluated, and numerical calculations of their performance, e.g. lower current density limits, are made. The modified small-signal input impedance is derived, and the layer is shown to be capacitive owing to its fluctuating charge storage. Transient response from the point of view of charge storage is also evaluated.
