Title :
Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI
Author :
Izawa, Ryuichi ; Kure, Tokuo ; Takeda, Eiji
Author_Institution :
Hitachi Ltd., Tokyo, Japan
fDate :
12/1/1988 12:00:00 AM
Abstract :
The gate-drain overlapped device (GOLD) structure is proposed to achieve high reliability and high performance in deep submicrometer MOSFETs. The GOLD device concept is different from that of drain-engineering methods such as the double-diffused drain (DDD) and lightly doped drain (LDD). GOLD eliminates the tradeoff between transconductance and breakdown voltage (hot-carrier, drain sustaining). The overlap effect of the GOLD devices is discussed using simulation and experiment. GOLD has a gate structure using a native oxide film (5-10 A) to obtain an overlapped fine structure. The process is also compatible with conventional LDD processes and is suitable for 0.3-0.5-μm-design-rule devices at 5-V operation, and 3-V operation
Keywords :
VLSI; field effect integrated circuits; integrated circuit technology; reliability; semiconductor technology; 0.3 to 0.5 micron; 3 V; 3-V operation; 5 V; 5 to 10 A; 5-V operation; SiO2-Si; deep submicrometer MOSFETs; deep submicrometer VLSI; gate structure; gate-drain overlapped device; high reliability; native oxide film; overlap effect; overlapped fine structure; scaling; submicron; Degradation; Fabrication; Gold; Hot carriers; Neodymium; Optimization methods; Power supplies; Transconductance; Very large scale integration; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
