Title :
A 0.45-V 300-MHz 10T Flowthrough SRAM With Expanded write/ read Stability and Speed-Area-Wise Array for Sub-0.5-V Chips
Author :
Chang, Meng-Fan ; Chen, Yung-Chi ; Chen, Chien-Fu
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
Capable of only solving the read-stability issue, many 8T-10T static RAM (SRAM) cells require extra write-assist circuits to achieve low supply voltage operation. This brief proposes a novel 10T SRAM cell and a hybrid-divided-block array to enhance the read-and-write stability while achieving a higher operating speed with a smaller area overhead for sub-0.5 V applications. A 16-Kb 128-row 10T flowthrough SRAM macro is fabricated using a 90-nm bulk-CMOS process. The 10T cell area is only 1.7 times the size of a 6T cell. The measured VDDmin for the 10T 16-Kb macro is 240 mV. The proposed 16-Kb macro can achieve 300-MHz random access operation at 0.45 V for a 0.5 V system platform.
Keywords :
SRAM chips; expanded write/read stability; flowthrough SRAM macro; frequency 300 MHz; hybrid-divided-block array; random access operation; read-and-write stability; read-stability issue; size 90 nm; speed-area-wise array; static RAM cell; supply voltage operation; voltage 0.45 V; voltage 0.5 V; voltage 240 mV; write-assist circuit; Arrays; Delay; Inverters; Low voltage; SRAM chips; Stability analysis; Transistors; Flowthrough; low voltage; read disturb; static random access memory (SRAM); write margin (WM);
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2010.2083130