Mechanisms of Threshold Voltage Shift in Polymorphous and Microcrystalline Silicon Bottom Gate Thin-Film Transistors

In this paper, we have studied the stability of polymorphous silicon (pm-Si:H) and μc-Si:F:H bottom gate thin-film transistors (TFTs) by combining degradation and relaxation experiments under various stress conditions. We report on polymorphous silicon (pm-Si:H) TFTs with ΔV_TH=1 V after 10 h of stress and μc-Si:F:H TFTs with superior stability, which show a ΔV_TH of only 0.05 V under stress conditions similar to those encountered in active-matrix operation regime (V_G=12 V and V_D=10 V). Relaxation studies show that the quality of the interface between silicon nitride and pm-Si:H (or μc-Si:F:H) controls the stability at short stress times. Interestingly, the deposition conditions of the semiconductor layer seem to modify the quality of the a-SiN:H and thus the stability of the interface.