DocumentCode :
1398818
Title :
Degradation of High- k /Metal Gate nMOSFETs Under ESD-Like Stress in a 32-nm Technology
Author :
Yang, Yang ; Gauthier, Robert J. ; Chatty, Kiran ; Li, Junjun ; Mishra, Rahul ; Mitra, Souvick ; Ioannou, Dimitris E.
Author_Institution :
Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
Volume :
11
Issue :
1
fYear :
2011
fDate :
3/1/2011 12:00:00 AM
Firstpage :
118
Lastpage :
125
Abstract :
The degradation of nMOSFETs induced by nondestructive electrostatic discharge-like (ESD-like) stress in a 32-nm bulk CMOS technology was studied using I- V characteristics and charge pumping measurements. The impact of stress on drain saturation current (Idsat), threshold voltage (Vt), transconductance peak (gm), and subthreshold swing (SS) is reported. For ESD stress applied on the drain, little degradation was observed until the device failed by drain-to-source filamentation. In contrast, for stress applied on the gate, positive ESD-like stress decreases Idsat and increases Vt of the nMOSFETs significantly, and the degradation increases with the effective gate oxide thickness. Different from positive bias temperature instability (PBTI) stress, the Vt shift depends on temperature rather weakly, which indicates a new dominant charge-trapping mechanism on the time scale of ESD events. In addition to the degradation of Vt and Idsat, the positive stress also caused significant damage to the Si/oxide interface in the nMOSFETs with thick gate oxide. The degradation of Idsat, Vt , gm, and SS under positive stress is more severe for devices with high-k gate compared to devices with SiON gate. It is also shown that the degradation induced by negative ESD-like stress applied on the gate is much smaller compared to positive stress. Finally, the impacts of the stress on the gate leakage current and on the the subsequent PBTI degradation kinetics are also studied.
Keywords :
CMOS integrated circuits; MOSFET; electrostatic discharge; high-k dielectric thin films; leakage currents; silicon compounds; CMOS technology; I-V characteristic; SiO2-SiON; charge pumping measurement; dominant charge-trapping mechanism; drain saturation current; drain-to-source filamentation; gate leakage current; gate oxide thickness; nMOSFET; nondestructive electrostatic discharge-like stress; positive bias temperature instability stress; size 32 nm; subthreshold swing; thick gate oxide; threshold voltage; time scale; transconductance peak; Charge trapping; defect generation; electrostatic discharge (ESD); high-$k$ dielectrics; metal gate; transmission line pulse (TLP);
fLanguage :
English
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
Publisher :
ieee
ISSN :
1530-4388
Type :
jour
DOI :
10.1109/TDMR.2010.2098407
Filename :
5661814
Link To Document :
بازگشت