Concurrent Device/Specification Cause–Effect Monitoring for Yield Diagnosis Using Alternate Diagnostic Signatures

In this paper, an efficient methodology for die level test-and-diagnosis for Analog/RF circuits is developed. The key contribution of this work lies in the ability to both determine the DUT specifications as well as the underlying Spice-level model parameters from the same DUT test response on a per chip basis, thereby providing quicker and higher diagnostic resolution. The test and diagnosis procedures are enabled by a new computationally efficient test stimulus generation algorithm that simultaneously targets test sensitivity and parameter model diagnosability. This allows cause-effect analysis to be performed that relates perturbations in the spice-level model parameters to the DUT performance metrics (specifications). Further, cause-effect diagnosis is achieved at a test cost comparable to prior testing schemes that target only pass/ fail classification of tested devices.