Title :
Interlaced diagonal-wise pipelined serial multiplier
Author :
Fanucci, L. ; Forliti, M.
Author_Institution :
CSMDR, Nat. Res. Council, Pisa, Italy
fDate :
10/12/2000 12:00:00 AM
Abstract :
A new two´s complement serial multiplier based on a pipelined diagonal-wise interlaced structure is presented. Two N×M multiplications are processed simultaneously, which is particularly useful for a high-throughput area-efficient complex number multiplier. Using the proposed scheme, an 8×8 bit complex multiplier prototype was realised in 0.2 μm standard cell CMOS technology with 1.6 Kgates complexity for a maximum operating frequency of 550 MHz
Keywords :
CMOS logic circuits; VLSI; high-speed integrated circuits; multiplying circuits; pipeline arithmetic; 0.25 micron; 550 MHz; area-efficient multiplier; complex multiplier prototype; complex number multiplier; pipelined diagonal-wise interlaced structure; pipelined serial multiplier; standard cell CMOS technology; twos complement serial multiplier;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20001252
