Internal chip ESD phenomena beyond the protection circuit

Author

Duvvury, Charvaka ; Rountree, Robert N. ; Adams, Olen

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

Volume

35

Issue

12

fYear

1988

fDate

12/1/1988 12:00:00 AM

Firstpage

2133

Lastpage

2139

Abstract

Input/output electrostatic discharge (ESD) circuit requirements call for good protection of the pin with respect to both the ground and the power bus pins. Although effective protection can be designed at the pin many cases of damage phenomena are known to occur internal to the chip beyond the protection circuit. Here, the issues of protection between V_DD and V_SS are discussed first. This is followed by examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design. Several illustrative actual case studies are reported to emphasize the internal chip ESD phenomena and their adverse effects

Keywords

CMOS integrated circuits; VLSI; electrostatic discharge; failure analysis; integrated circuit technology; overvoltage protection; CMOS; ESD damage; ESD immunity; I/O pin protection; VLSI; adverse effects; case studies; circuit requirements; damage beyond protection circuit; damage phenomena; degradation phenomena; effective protection; electrostatic discharge; examples; internal chip ESD phenomena; internal chip layout; protection between V_DD and V_SS; protection between power bus lines; protection circuit performance; CMOS technology; Circuit testing; Degradation; Electrostatic discharge; Instruments; Internal stresses; Pins; Protection; Semiconductor diodes; Variable structure systems;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.8787

Filename

8787