Systolic architectures for the computation of the discrete Hartley and the discrete cosine transforms based on prime factor decomposition

Author

Chakrabarti, Chaitali ; JáJá, Joseph

Author_Institution

Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA

Volume

39

Issue

11

fYear

1990

fDate

11/1/1990 12:00:00 AM

Firstpage

1359

Lastpage

1368

Abstract

Two-dimensional systolic array implementations for computing the discrete Hartley transform (DHT) and the discrete cosine transform (DCT) when the transform size N is decomposable into mutually prime factors are proposed. The existing two-dimensional formulations for DHT and DCT are modified, and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting architecture is fully pipelined with no control units. The hardware design is based on bit serial left to right MSB (most significant bit) to LSB (least significant bit) binary arithmetic

Keywords

fast Fourier transforms; parallel architectures; binary arithmetic; discrete Hartley; discrete cosine transforms; hardware design; prime factor decomposition; systolic architectures; two-dimensional systolic arrays; Arithmetic; Computer architecture; Delay estimation; Discrete cosine transforms; Discrete transforms; Hardware; Helium; Signal processing algorithms; Systolic arrays; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.61045

Filename

61045