A simulation model for electromigration in fine-line metallization of integrated circuits due to repetitive pulsed currents

The design trend of digital very-large-scale integrated circuits (VLSI) toward higher power dissipation per chip, higher switching speeds, and smaller cross-section interconnect metallization lines has increased concern about the reliability of these devices with respect to electromigration as a failure mechanism. A simulation model for the major physical processes that influence the development and progression of electromigration damage due to pulsed electric currents is described. A comparison of model behavior to that observed experimentally for steady current (DC) stressing is made, and it is concluded that the model may provide a reasonable prediction of expected behavior under pulsed current stressing. However, experimental verification of the model is required before it can be used with assurance for design guidance