DocumentCode
1400034
Title
Hysteresis cycle in the latch-up characteristic of wide CMOS structures
Author
Selmi, Luca ; Sangiorgi, Enrico ; Crisenza, G. ; Re, D. ; Ricco, Bruno
Author_Institution
Dept. of Electron., Bologna Univ., Italy
Volume
9
Issue
5
fYear
1988
fDate
5/1/1988 12:00:00 AM
Firstpage
214
Lastpage
216
Abstract
Experimental results are interpreted in terms of a simple lumped-element model that is also used to reproduce the hysteresis phenomenon with discrete components. The hysteresis is related to a three-dimensional (3-D) nonuniformity in the current distribution. Such hysteresis can lead to an erroneous evaluation of latchup parameters, such as the holding current density.<>
Keywords
CMOS integrated circuits; current distribution; hysteresis; integrated circuit technology; 3D current distribution nonuniformity; holding current density; hysteresis phenomenon; latch-up characteristic; lumped-element model; wide CMOS structures; Circuit testing; Current density; Current distribution; Doping; Equivalent circuits; Hysteresis; Physics; Semiconductor device modeling; Two dimensional displays; Voltage;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.694
Filename
694
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