Hardware implementation of a pulse-stream neural network

The authors describe the design and test of an artificial neural network, using a pulse-stream approach, that is implemented using BiCMOS technology. Networks are constructed from arrays of customised neuron chips and synapse chips. The neuron chip uses novel circuitry to implement an accurate sigmoid transfer characteristic. The synapse chip uses a new pulse-stream implementation of the differential amplifier and requires only five transistors to produce a linear multiplier. Measured results from the chips show that the neuron has an accurate sigmoid transfer characteristic and gradient suitable for the error backpropagation learning algorithm. The synapse has excellent 1% linearity and properties suitable for multiplication. The chips have been used to implement a three-layer artificial neural network which has been tested using hard learning problems