Title :
Electrical limitations of advanced LOCOS isolation for deep submicrometer CMOS
Author :
Lutze, Jeffrey W. ; Krusius, Peter J.
Author_Institution :
Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
fDate :
2/1/1991 12:00:00 AM
Abstract :
Limitations to advanced local oxidation of silicon (LOCOS) based dielectric isolation of the poly buffer type are examined by fabricating CMOS devices with active area widths and spaces to 200 nm. Measured results show that device width scaling to 400 nm is possible using the retrograde-well process. The impact of narrow-channel effects, field oxide thinning, and drain-induced barrier lowering (DIBL) of the field oxide transistors on deep submicrometer CMOS has been quantified. For a retrograde-well process the narrow-channel effect is minimal for active device widths to 0.4 μm. DIBL is shown to limit the active device spacing to about 0.8 μm. SUPREM-4 and PISCES-2B simulations are utilized to illustrate the mechanism for the loss of isolation
Keywords :
CMOS integrated circuits; insulated gate field effect transistors; oxidation; semiconductor device models; PISCES-2B simulations; SUPREM-4 simulation; Si dielectric isolation; active device widths; advanced LOCOS isolation; advanced local oxidation; deep submicrometer CMOS; device width scaling; drain-induced barrier lowering; electrical limitations; field oxide thinning; field oxide transistors; isolation loss mechanism; narrow-channel effect; retrograde-well process; CMOS process; CMOS technology; Implants; Isolation technology; Nanofabrication; Numerical analysis; Oxidation; Senior members; Temperature; Transistors;
Journal_Title :
Electron Devices, IEEE Transactions on
