Three-phase dual-output six-switch inverter

A novel dual-output six-switch inverter topology is proposed in this study for independently supplying two three-phase loads. This inverter employs less number of semiconductor devices compared with former dual-output inverters proposed so far in the literature. Reducing the number of switches and hence drive and control circuits may result in a reduction in overall cost of the system, may reduce its semiconductor power loss and as a result increases efficiency and reliability especially in applications with low and medium voltage and power ratings. The new configuration is introduced and carrier-based pulse-width modulation (PWM) schemes for its two defined modes of operation (constant frequency and variable frequency modes) are developed. Analysis of sizing of the DC-link capacitors is also performed so as to minimise the DC-link voltage ripple and to reduce the value of DC-link capacitors. Furthermore, loss profile of the system is studied and the results are compared with counterpart topologies. Simulation and experimental results are presented to verify the authenticity of the theoretical model.