Title :
Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs
Author :
Kaga, Tom ; Kure, Tokuo ; Shinriki, Hiroshi ; Kawamoto, Yashifumi ; Murai, Fumio ; Nishida, Takashi ; Nakagome, Yoshinobu ; Hisamoto, Digh ; Kisu, Teruaki ; Takeda, Eiji ; Itoh, Kiyoo
Author_Institution :
Hitachi Ltd., Tokyo, Japan
fDate :
2/1/1991 12:00:00 AM
Abstract :
A self-aligned stacked-capacitor cell called the CROWN cell (a crown-shaped stacked-capacitor cell), used for experimental 64-Mb-DRAMs operated at 1.5 V, has been developed using 0.3-μm electron-beam lithography. This memory cell has an area of 1.28 μm2. The word-line pitch and sense-amplifier pitch of this cell are 0.8 and 1.6 μm, respectively. In spite of this small cell area, the CROWN cell has a large capacitor surface area of 3.7 μm2 because (1) it has a crown-shaped capacitor electrode, (2) its capacitor is on the data line, and (3) it has a self-aligned memory cell fabrication process and structure. The large capacitor area and a Ta2O5 film equivalent to a 2.8-nm SiO2 film ensure a large storage charge of 33 fC (storage capacitance equals 44 fF) for 1.5-V operation. A small CROWN cell array and a memory test circuit were successfully used to achieve a basic DRAM cell operation
Keywords :
DRAM chips; MOS integrated circuits; electron beam lithography; integrated circuit technology; 0.3 micron; 1.5 V; 44 fF; 64 Mbit; CROWN cell; CVD; DRAM cell operation; Si-SiO2; Ta2O5 film; crown-shaped capacitor electrode; electron-beam lithography; memory test circuit; self-aligned memory cell fabrication process; self-aligned stacked-capacitor cell; sense-amplifier pitch; storage capacitance; word-line pitch; Associate members; Capacitance; Capacitors; Circuit testing; Electrodes; Fabrication; Lithography; Power supplies; Random access memory; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
