Simulation of hot-electron trapping and aging of nMOSFETs

An analysis of the degradation of 1-μm-gate-length nMOSFET operating under normal biasing conditions at room temperature is reported. A physical model of hot-electron trapping in SiO₂ is developed and is used with a two-dimensional device simulator (PISCES) to simulate the aging of the device under normal biasing conditions. The initial degradation takes place near the high-field drain region and spreads over a long time toward the source. The degraded I-V characteristics of the MOSFET exhibit a shift of the pinchoff voltage and a compression of the transconductance, for forward and reverse operation, respectively. The simulated degradation qualitatively agrees with reported experimental data. Large shifts of the MOSFET threshold voltage for small drain voltages result as the degradation is spreading toward the source. An inflection point arises for low gate and drain voltages in the drain I-V characteristics of the MOSFET. This inflection point originates when the pinchoff of the channel-induced trapped-electron charge is overcome by the drain voltage; the drain acts as a second gate (short-channel effect). The estimation of the device´s lifetime by simulated aging is proposed