Characterization of bipolar snapback and breakdown voltage in thin-film SOI transistors by two-dimensional simulation

Author

Armstrong, G.A. ; Davis, John R. ; Doyle, Aiden

Author_Institution

Dept. of Electr. & Electron. Eng., Queen´´s Univ., Belfast, UK

Volume

38

Issue

2

fYear

1991

fDate

2/1/1991 12:00:00 AM

Firstpage

328

Lastpage

336

Abstract

A two-dimensional finite-difference simulator for silicon-on-insulator (SOI) MOSFETs is presented. The simulator is derived from the MINIMOS4 simulator and incorporates additional features which permit the characterization of the bipolar snapback effect, which has been observed as a limiting feature in ultra-thin-film transistors. The snapback effect is illustrated as a hysteresis mechanism whereby, for a given bias condition, there are two different solutions to the semiconductor equations, depending on the starting condition. Examples of the application of the simulator to predict breakdown voltage in submicrometer devices are considered. Excellent agreement with measured values of breakdown voltage has been achieved for submicrometer n-channel transistors, both with and without the use of lightly doped drains

Keywords

MOS integrated circuits; electric breakdown of solids; insulated gate field effect transistors; semiconductor device models; thin film transistors; 2D simulator; MINIMOS4; MOSFETs; bias condition; bipolar snapback; breakdown voltage; finite-difference simulator; hysteresis mechanism; lightly doped drains; n-channel transistors; semiconductor equations; submicrometer devices; submicron device; thin-film SOI transistors; two-dimensional simulation; Circuits; Finite difference methods; Hysteresis; Impact ionization; MOSFETs; Predictive models; Silicon on insulator technology; Thin film transistors; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.69914

Filename

69914