Title :
Chain grouping: a method for partitioning loops onto mesh-connected processor arrays
Author :
Tsanakas, P. ; Koziris, N. ; Papakonstantinou, G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Greece
Abstract :
This paper presents Chain Grouping, a new low complexity method for the problem of partitioning the loop iteration space into groups with little intercommunication requirements, for mapping onto mesh-connected architectures. First, the iterations are scheduled in time, according to the hyperplane method, taking into consideration the minimum time displacement. Then, the iteration space is divided into discrete groups of related iterations, which are assigned to different processors, while preserving the optimal completion time. Chain Grouping is based on clustering together neighboring uniform chains of iterations, formed by a particular dependence vector. This vector will be proven as the best among all to reduce the total communication requirements. Inside every group, the optimal hyperplane scheduling is preserved and references to intragroup iterations are considerably increased. The partitioned groups are afterward assigned to meshes of processors. The resulting space mapping maximizes processor utilization and cuts down overall communication delays while preserving the optimal hyperplane time schedule.
Keywords :
parallel algorithms; parallel architectures; Chain Grouping; hyperplane method; loop grouping; mesh-connected architectures; mesh-connected processor arrays; orthogonal projection; partitioning loops; partitioning the loop iteration space; uniform chains of iterations; Computer Society; Computer architecture; Concurrent computing; Delay effects; Parallel architectures; Parallel processing; Processor scheduling; VLIW; Vectors;
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on