A versatile digital signal annunciator for monitor/control panel instrumentation

An application-specific integrated circuit (ASIC) design for a four-signal annunciator chip is developed. The design incorporates the ability to select three modes of operation of the sound alarm, economic lamp logic for visual indication, an all-digital built-in widely adjustable delay network for the sound alarm, operator acknowledge, autoacknowledge, two separate tones for the sound alarm-one to identify signal detection and the other to identify signal clearance-and logic circuits for cascading any number of chips and robust glitch-free operation. A 3-μm CMOS standard-cell-based layout design in Caltech Intermediate Four (CIF) is obtained. The core area and chip area are 6050 μm×4904 μm and 7426 μm×6188 μm, respectively, and the gate complexity is equivalent to 1537 in two-input NAND gates. Fan-out delay is 34.40 ns, and the estimated power dissipation is ≈11 mW