DocumentCode
1401175
Title
A reconfigurable tree architecture with multistage interconnection network
Author
Biswas, Nripendra N. ; Srinivas, S.
Author_Institution
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Volume
39
Issue
12
fYear
1990
fDate
12/1/1990 12:00:00 AM
Firstpage
1481
Lastpage
1485
Abstract
A novel approach to the design of a reconfigurable tree architecture is presented. The architecture is implemented with an augmented shuffle-exchange multistage interconnection network and is capable of assuming N distinct binary tree configurations, where N is the number of processing elements (PEs) in the system. The novel features of the architecture include fast switching from one configuration to another, simplified hardware in the PEs and the switching network, and simple routing control
Keywords
computer architecture; multiprocessor interconnection networks; augmented shuffle-exchange; distinct binary tree configurations; multistage interconnection network; processing elements; reconfigurable tree architecture; routing control; switching network; Arithmetic; Computer architecture; Fault detection; Iterative methods; Logic arrays; Logic testing; Multiprocessor interconnection networks; Switches; Systolic arrays; Very large scale integration;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.61069
Filename
61069
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