• DocumentCode
    1401480
  • Title

    Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches

  • Author

    Pomeranz, Irith ; Reddy, Sudhakar M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
  • Volume
    17
  • Issue
    3
  • fYear
    1998
  • fDate
    3/1/1998 12:00:00 AM
  • Firstpage
    269
  • Lastpage
    278
  • Abstract
    The use of three-valued logic for the fault simulation of synchronous sequential circuits may incur a loss of accuracy that would cause the fault coverage to be underestimated. In addition, loss of fault coverage may occur due to the test strategy employed. These problems were previously alleviated at the cost of a high computational complexity. We present an observation that allows us to alleviate loss of fault coverage in many cases, at a computational cost similar to conventional three-value fault simulation. Based on this observation, we propose a fault simulation procedure that uses a conventional fault simulation procedure enhanced by a simple implication procedure. The proposed fault simulation procedure identifies faults that are detected under the multiple observation time approach and under a special case of this approach, called the restricted multiple observation time approach. The results of the proposed simulation procedure are compared to the results of a previously proposed procedure to demonstrate its effectiveness. Heuristics to guide a test generation procedure whose test sequences are effective for faults that can only be detected under the multiple observation time approach are also described
  • Keywords
    automatic testing; fault diagnosis; integrated circuit testing; logic testing; multivalued logic; sequential circuits; computational cost; fault simulation; implication procedure; low-complexity fault simulation; multiple observation time; restricted multiple observation time; synchronous sequential circuits; test generation procedure; test strategy; three-valued logic; Circuit faults; Circuit simulation; Circuit testing; Computational complexity; Computational efficiency; Computational modeling; Costs; Fault detection; Fault diagnosis; Sequential circuits;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.700724
  • Filename
    700724