Title :
A 533-MHz BiCMOS superscalar RISC microprocessor
Author :
Maier, Cliff A. ; Markevitch, James A. ; Brashears, Cheryl Senter ; Sippel, Tim ; Cohen, Earl T. ; Blomgren, Jim ; Ballard, James G. ; Pattin, Jay ; Moldenhauer, Viki ; Thomas, Jeffrey A. ; Taylor, George
Author_Institution :
Exponential Technol., San Jose, CA, USA
fDate :
11/1/1997 12:00:00 AM
Abstract :
This 533-MHz BiCMOS very large scale integration (VLSI) implementation of the PowerPC architecture contains three pipelines and a large on-chip secondary cache to achieve a peak performance of 1600 MIPS. The 15 mm×10 mm die contains 2.7 M transistors (2M CMOS and 0.7 M bipolar) and dissipates less than 85 W. The die is fabricated in a six-level metal, 0.5-μm BiCMOS process and requires 3.6 and 2.1 V power supplies
Keywords :
BiCMOS digital integrated circuits; VLSI; microprocessor chips; pipeline processing; reduced instruction set computing; 0.5 micron; 1600 MIPS; 2.1 V; 3.6 V; 533 MHz; 85 W; BiCMOS superscalar RISC microprocessor; PowerPC architecture; VLSI implementation; onchip secondary cache; pipelines; BiCMOS integrated circuits; CMOS logic circuits; Coupling circuits; Logic circuits; Microarchitecture; Microprocessors; Pipelines; Process design; Reduced instruction set computing; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
