Title :
A semidigital dual delay-locked loop
Author :
Sidiropoulos, Stefanos ; Horowitz, Mark A.
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
fDate :
11/1/1997 12:00:00 AM
Abstract :
This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2π) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8-μm CMOS technology is described. The prototype achieves an operating range of 80 kHz-400 MHz. At 250 MHz, its peak-to-peak jitter with quiescent supply is 68 ps, and its jitter supply sensitivity is 0.4 ps/mV
Keywords :
CMOS integrated circuits; delay circuits; jitter; 0.8 micron; 80 kHz to 400 MHz; CMOS chip; clock generation; jitter; operating range; phase interpolation; phase shift; semidigital dual delay-locked loop architecture; CMOS technology; Clocks; Delay; Interpolation; Jitter; Phase detection; Phase frequency detector; Phase locked loops; Prototypes; Voltage control;
Journal_Title :
Solid-State Circuits, IEEE Journal of
