Title :
A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme
Author :
Tsukude, Masaki ; Kuge, Shigehiro ; Fujino, Takeshi ; Arimoto, Kazutami
Author_Institution :
Memory IC Div., Mitsubishi Electr. Corp., Hyogo, Japan
fDate :
11/1/1997 12:00:00 AM
Abstract :
A charge-transfer presensing scheme (CTPS) for 0.8-V array operation with a 1/2 Vcc bit-line precharge achieves a five times larger readout voltage and 40% improvement in sensing speed compared with conventional sensing schemes. Operation over a 1.2- to 3.3-V range is achieved. A nonreset row block control scheme (NRBC) for power-consumption improvement in data-retention mode is proposed which decreases the charge/discharge number of the row block control circuit. By combining CTPS and NRBC, the data-retention current is reduced by 75%
Keywords :
CMOS memory circuits; DRAM chips; 0.8 V; 1.2 to 3.3 V; CMOS dynamic RAM; bit-line precharge; charge-transfer presensing scheme; data-retention mode; low-power DRAM; nonreset row block control scheme; power-consumption improvement; row block control circuit; wide voltage-range operation; Batteries; Circuits; Costs; Logic arrays; Logic devices; Low voltage; Multimedia systems; Power supplies; Random access memory; Standardization;
Journal_Title :
Solid-State Circuits, IEEE Journal of
