Title :
On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM
Author :
Tanoi, Satoru ; Tokunaga, Yasuhiro ; Tanabe, Tetsuya ; Takahashi, Kazuhiko ; Okada, Atsuhiko ; Itoh, Masahiro ; Nagatomo, Yoshiki ; Ohtsuki, Yoshio ; Uesugi, Masaru
Author_Institution :
VLSI R&D Center, Oki Electr. Ind. Co. Ltd., Tokyo, Japan
fDate :
11/1/1997 12:00:00 AM
Abstract :
An on-wafer built-in self-test (BIST) technique has been developed to implement a 200 Gb/s failed-bit search for a 1-Gb DRAM. The BIST circuits include a 4-kb very-long word bus and an on-wafer test management unit to probe DRAM arrays and compress test results. The 1-Gb DRAM is fabricated as a test device using a 0.16-μm CMOS technology. As a result, the BIST reduces the wafer test time to less than 1/100 that of bit-by-bit testing
Keywords :
CMOS memory circuits; DRAM chips; built-in self test; integrated circuit testing; 0.16 micron; 1 Gbit; 200 Gbit/s; CMOS technology; DRAM array probing; built-in self-test technique; dynamic RAM; failed-bit search; on-wafer BIST; onwafer test management unit; very-long word bus; Automatic testing; Built-in self-test; CMOS technology; Circuit testing; Costs; Probes; Random access memory; Research and development; Sequential analysis; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
