A restructurable VLSI robotics vector processor architecture for real-time control

The authors propose a restructurable architecture based on a VLSI robotics vector processor (RVP) chip. It is specially tailored to exploit parallelism in the low-level matrix/vector operations characteristic of the kinematics and dynamics computations required for real-time control. The RVP is composed of three tightly synchronized 32-bit floating-point processors to provide adequate computational power. Besides adder and multiplier units in each processor, the RVP contains a triple register-file, dual shift network, and dual high-speed input/output (I/O) channels to satisfy the storage and data movement demands of the computations targeted. Efficiently synchronized multiple-RVP configurations, which may be viewed as variable very-long-instruction-word architectures, can be constructed and adapted to match the computational requirements of specific robotics computations. The use of the RVP is illustrated through a detailed example of the Jacobian computation, demonstrating good speedup over conventional microprocessors even with a single RVP. The RVP has been developed to be implementable on a single VLSI chip using 1.2-μm CMOS technology, so that a single-board multiple-RVP system can be targeted for use on a mobile robot