DocumentCode :
1402534
Title :
Characterization of an n-p-n structure under ESD stress and proposed electrical model
Author :
Tailliet, François ; Chante, Jean-peirre
Author_Institution :
SGS-Thomson, Rousset, France
Volume :
37
Issue :
4
fYear :
1990
fDate :
4/1/1990 12:00:00 AM
Firstpage :
1111
Lastpage :
1120
Abstract :
The real-time electrical behavior of an n-p-n electrostatic discharge (ESD) protection structure is studied. The fabrication process is a classical CMOS n-well. Measurement difficulties are described, and quantitative results are emphasized. Successive conduction mechanisms for both polarities, such as diffusion delays and thermal runaway, are demonstrated by experiments. A simple qualitative model that agrees with the measurements is proposed. The results also explain many in-circuit ESD failures due to unwanted n-p-n structures and allow the creation and justification of efficient ESD-protective design rules
Keywords :
CMOS integrated circuits; electrostatic discharge; equivalent circuits; integrated circuit testing; protection; semiconductor device models; CMOS n-well; ESD stress; ESD-protective design rules; conduction mechanisms; diffusion delays; electrical model; electrostatic discharge; fabrication process; in-circuit ESD failures; monolithic IC; n-p-n structure; protection structure; real-time electrical behavior; thermal runaway; CMOS technology; Circuit testing; Current measurement; Electrostatic discharge; Electrostatic measurements; Probes; Protection; Semiconductor device modeling; Stress; Voltage measurement;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.52450
Filename :
52450
Link To Document :
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