DocumentCode
1402628
Title
Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation
Author
Chang, Ik Joon ; Park, Sang Phill ; Roy, Kaushik
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume
45
Issue
2
fYear
2010
Firstpage
401
Lastpage
410
Abstract
Supply voltage scaling is one of the easiest ways to reduce energy dissipation. Therefore, researchers have considered subthreshold logic as a promising option to achieve ultra low energy dissipation. However, circuit propagation delay is extremely sensitive to PVT variations under subthreshold operation. Hence, large delay margin is required for successful operation of conventional synchronous designs. Since leakage energy contributes to a substantial portion of total energy dissipation in subthreshold operation, the leakage energy dissipated for the required delay margin degrades energy efficiency significantly. In addition, even small intra-die variations result in large clock skew and hence, it is difficult to efficiently handle timing issues such as the setup and the hold time violations. In this work, we explore asynchronous design approach to address these challenges in subthreshold operation. We employ critical-path replica to generate completion signals of combinational logic blocks and use classical four-phase handshaking for communication between pipeline flip-flops. Since the proposed design approach uses only local clock buffers, it is easier to handle timing problems compared to synchronous designs. We compared iso-yield minimum energy dissipation of two design approaches (synchronous and asynchronous) in an inverter chain. Despite leakage overhead due to pad delay of critical-path delay line and ?return-to-zero? time of four-phase handshaking, the proposed asynchronous design shows 71% energy savings compared to its synchronous counterpart. To demonstrate subthreshold operation of the proposed design approach, we fabricated an 8-tap FIR filter in 90 nm CMOS. Measured oscilloscope plots of handshaking and output bus signals show that the design operates successfully below 300 mV. We also measured energy consumption of the FIR filter from 19 test chips-the average was 4.64 pJ and the standard deviation was 0.3526 pJ.
Keywords
FIR filters; asynchronous circuits; combinational circuits; flip-flops; logic design; FIR filter; asynchronous design; asynchronous logic; circuit propagation delay; combinational logic block; critical-path delay line; energy dissipation; energy-efficient subthreshold operation; four-phase handshaking; leakage energy; pipeline flip-flops; process-tolerant subthreshold operation; size 90 nm; subthreshold logic; supply voltage scaling; Clocks; Delay; Energy dissipation; Energy efficiency; Finite impulse response filter; Logic; Process design; Semiconductor device measurement; Timing; Voltage; Asynchronous logic; CMOS digital circuit design; low power VLSI; subthreshold logic design;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2009.2036764
Filename
5405151
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