An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 $\mu$ m CMOS

A pipelined analog-to-digital converter (ADC) uses switched-capacitor stages that settle in two steps that occur sequentially in time. The first step of settling places charge onto the load capacitance using charge pumps, and the second fulfills the settling requirements using typical negative feedback around an operational amplifier. Hence, the design combines the efficiency of a fast charge-transfer phase with the gain and noise-immunity advantages of amplifier-driven settling. Improved conversion efficiency results from a higher ratio of current delivered to the load to that consumed in static biasing. Additional circuitry constrains critical amplifier node voltages during the charge transfer, facilitating a graceful transition to amplifier-driven settling. The two-step settling technique is demonstrated in a 2.5 bit/stage 10-bit pipelined ADC that consumes 11.1 mW while sampling a 21.3 MHz input signal at 42 MS/s. The resulting SNDR is 55.6 dB (ENOB = 8.94) and the SFDR is 67.5 dB.