Title :
An integrated CMOS distributed amplifier utilizing packaging inductance
Author :
Sullivan, Patrick J. ; Xavier, Bernard A. ; Ku, Walter H.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
fDate :
10/1/1997 12:00:00 AM
Abstract :
An integrated CMOS distributed amplifier is presented. The required inductance needed for the distributed waveguide structure is realized by the parasitic packaging inductance of a plastic surface-mount package. A fully packaged three-stage distributed amplifier fabricated in a 0.8-μm CMOS process is presented. The distributed amplifier has a unity gain cutoff frequency of 4.7 GHz, a gain of 5 dB, with a gain flatness of ±1.2 dB over the 300-kHz to 3-GHz band. At a frequency of 2 GHz the amplifier has an input referred third-order intercept point of +15 dBm and an input referred 1-dB compression point of +7 dBm. The amplifier consumes 18 mA from a 3.0-V supply. The distributed amplifier is matched to 50 Ω at the input and output and has a maximum input voltage standing-wave ratio (VSWR) of 1.7:1, and a maximum output VSWR of 1.3:1 over the 300 kHz to 3 GHz band. The amplifier has a noise figure of 5.1 dB at 2 GHz
Keywords :
CMOS analogue integrated circuits; distributed amplifiers; inductance; integrated circuit packaging; plastic packaging; surface mount technology; 0.8 micron; 18 mA; 3.0 V; 300 kHz to 3 GHz; 5 dB; 5.1 dB; compression point; distributed waveguide; gain; gain flatness; integrated three-stage CMOS distributed amplifier; noise figure; parasitic packaging inductance; plastic surface mount package; third-order intercept point; unity gain cutoff frequency; voltage standing-wave ratio; CMOS integrated circuits; CMOS process; CMOS technology; Distributed amplifiers; Gallium arsenide; Inductance; MOSFET circuits; Plastic integrated circuit packaging; Plastic packaging; Substrates;
Journal_Title :
Microwave Theory and Techniques, IEEE Transactions on
